gEDA GNU Schematic Capture Ales Hvezda Copyright © 1998 by Ales Hvezda This document can be freely redistributed according to the terms of the GNU General Public License. _________________________________________________________________ Table of Contents 1. [1]Introduction 2. [2]The Basics [3]What is Schematic Capture? [4]Key concepts [5]Components [6]Attributes [7]Pins [8]Nets [9]Buses [10]Schematic Sheet _________________________________________________________________ Chapter 1. Introduction gEDA stands for GNU Electronic Design Automation (EDA). It is a collection of tools for doing schematic capture, circuit simulation, printed circuit board layout and any other tasks involving electronic circuits. Basically all the tools which are part of gEDA are used to automate the design process of electronic circuits. Both analog and digital designers use EDA tools to simplify the design process. What makes gEDA unique when compared to commercial tools is that all the of the source and file specifications are placed under the GNU Public License (GPL) version 2.0. These leads to a open (as in the no secrets and no surprises type of "open"), flexible, extensible, and readily available toolset for doing EDA. When this particular document was last revised only the schematic capture (gschem), a crude netlist generation (gnetlist), a MOS simulator (gmos), and an analog waveform viewer (gwave) existed. This document focuses on gschem. Schematic capture is one way in which circuit designers document or describe a particular design. This document will describe what schematic capture and how to use gschem. There are several other ways of documenting a design such as using a Hardware Description Language (HDL) such as VHDL or Verilog. Other available techniques such as graphical state diagramming or graphical flowcharts are sometimes used as well. These techniques will not be covered, only schematic capture is addressed by this document. This document will focus on gate level and component level schematic capture (which is what the author is most familiar with). Gschem was not originally design for VLSI or ASIC design but might eventually end up supporting such designs. It should also be noted that gEDA and everything associated with it is consider "alpha" and lacks a lot of the fine polishing of a piece of GNU software. It may dump core and/or it may consume every resource in sight. The software is provided with the usual NO WARRANTY disclaimers. This document is also consider "alpha" so there may be errors. If you find something questionable please be sure to e-mail ahvezda@geda.seul.org. Many thanks to everybody who has help with gEDA's development. This includes all the people suggested features and/or contributed code to the gEDA project. Without these people gEDA would not be where it is today. _________________________________________________________________ Chapter 2. The Basics What is Schematic Capture? Schematic capture is a fancy name for the ability to draw and layout circuits using a computer. Standard symbols are used to represent the various gates and components which are interconnected by nets (wires). There are several characteristics which a program must have to be able to do schematic capture: * The awareness of the electrical properties of components, nets, and pins. * Hierarchical design (having components represent some abstracted functionality). * The ability to associate attributes with nets and components. * Generate netlists from the schematic. The ability to generate netlists is not part of gschem, but gnetlist takes care of this. As of the last revision of this document, gschem meets all of the above requirements (some of the requirements are just barely met, so much work is still required). So how do people use schematic capture software? These people usually have to design electronic circuits (either for their jobs or for fun). Since we are in the age of Computer Aided Design (CAD), they use EDA tools to make the design experience easier (and a whole lot more enjoyable). After a design engineer understands the specifications and has a mental image or rough draft for the circuit he/she needs to design, the engineer sits down in front of a computer running schematic capture software to lay out the circuit(s) (assuming the circuit is best described by a schematic and not a HDL). The engineer places the required components on a schematic sheet connecting the pins with nets or buses. Attributes are attached to these primitives to convey additional information and details. The next sections go into detail of what these various pieces are and how they fit together. _________________________________________________________________ Key concepts This section describes key concepts such as what primitive objects are typically associate with schematic capture programs as well as definitions of term which can have multiple and/or confusing meanings. _________________________________________________________________ Components A component is a collection of lines, boxes, circles, text, and pins which represent, symbolize, or abstract some aspect of a design. Components can be gates (like a TTL NAND gate), block diagram boxes, a graphical representation of another schematic sheet, or some electrical entity (such as ground or power). A component typically does not represent a physical package (like a 7400 Integrated Circuit (IC)) but there is no reason it cannot (the components which are part of gEDA do not represent physical packages). Figure 2.1 shows a selection of simple gates, a flipflop, a few analog components, and a few IEC417 blocks. Figure 2-1. A selection of components [INLINE] Components are sometimes called parts, complex objects, or symbols. All of these names refer to the same concept. This document will only use the term "component". _________________________________________________________________ Attributes Attributes are additional pieces of information connected to a primitive object such as a component, net, pin, or misc graphic. Attributes specify information which is usually required by netlisters or other design tools. Attributes are nothing more then text items which take on the form "name=value". Examples of attributes include slot numbers (which individual gate a component references in a physical IC package), urefs (a name of an instance of a component like U100 or U201), logical names for nets and buses, pin numbers, or values of analog devices (such a 10 Ohms for resistors). Some attributes are visible (such as pin names and urefs), and some attributes are invisible such as specific device information. Figure 2.2 shows a single TTL NAND gate with all attributes visible. Figure 2-2. A component with all attributes visible [INLINE] gEDA uses an attribute system to convey the required additional information which needs to be associated with the various schematic objects. An attribute is connected to the object which makes the most sense to have that attribute (such as the pin which needs a pin number attribute), but sometimes there isn't a logical place for an attribute to be attached (such as the device attribute or slot information attributes), so an arbitrary graphic item is used as the object to receive the attribute. Which attributes are required by which objects will be described in the symbol creation and gnetlist documentation. (*TBD*) Attributes are sometimes known as property lists. *Any other names from the different EDA tools*? Even though property lists and attributes are the same thing, gEDA and this document uses the term "attributes" as the term for the above described concept. _________________________________________________________________ Pins Pins are the interface primitives for components. They interface a component to the rest of the world. Basically, components have pins where an input or output is needed. Pins in schematic capture are usually equivalent to the pins on a IC, but sometimes that is not the case. Pins can also be used to connect a "black box" (which is a symbol representing something) to the rest of the world. These black boxes sometimes do not have schematic underneath (ie they don't represent another sub circuit) and just symbolize something non-material. *better wording for all this*. On some schematic capture systems pins are a single point. In gschem a pin is a line, which can be visually (and printed) thin or thick (doesn't matter which, that decision is a matter of taste). In a future release of gEDA pins might be single point and another entity will represent the pin, but for now pins in gschem are special lines. Typically only one end of the pin can be connected to another pin or net (even though at the last revision of this document, pins can be connected to at both ends, which is a bug). The other end of the pin is the component side of the connection. Nets are used to connect the various pins on components to pins on other components. _________________________________________________________________ Nets Nets are the schematic capture term for electrical wires. Nets interconnect components (technically they interconnect the pins on components). Nets can connect to other nets as well. Nets do not necessary have a one-to-one correspondence to physical wires in a design (taking the nets in a schematic and converting them to the physical wires is the responsibility of the netlister/generator). Figure 2.3 shows a few nets and various styles available for nets in gschem. Figure 2-3. Nets and the various styles of endpoint and midpoint cues [INLINE] Nets can be shown (and printed) either as thin or thick lines. A single net has two endpoints. At the endpoints, gschem displays visual cues which help in determining if a net is connected (the visual cues disappear if this occurs) or if a net is dangling/not connected (the visual cues are shown). When nets intersect another net in the middle then a midpoint visual cue is displayed. Figure 2.3a shows a thin net with filled endpoint cues. Figure 2.3b shows a thick net with empty endpoint cues. Figure 2.3c shows a thin net with X (crossing) endpoint cues. Figure 2.3d shows a few thick nets with empty endpoint and filled/empty midpoint cues. These endpoint/midpoint cues are useful to indicate when nets are electrically connected or disconnected. The cues are also useful to see if nets which are crossing are connected or not. Figure 2.3e shows some nets which are crossing and are not electrically connected. Figure 2.3f shows some nets which are electrically connected. Contrary to what Figure 2.3 indicates, you can only have one type of net thickness and visual cue style per gschem invocation. _________________________________________________________________ Buses Buses in schematic capture represent many nets bundled together in a single thick line. Buses connect nets together. Buses cannot be connected to pins directly, because all connections (the nets) to buses must have labels (net labels). You cannot label a pin of a component. All of the above is speculation since gschem DOES NOT (yet) have a bus primitive. Expect it to appear soon. Please don't ask Ales how to draw buses, cause then Ales will have to hurt you. :-) _________________________________________________________________ Schematic Sheet A schematic sheet or page is the collection of all of the above mentioned primitives. Typically a large design does not fit on a single schematic sheet so it spans several sheets/pages. Gschem has facilities for dealing with multiple pages. References 1. file://localhost/tmp/@31281.2#AEN29 2. file://localhost/tmp/@31281.2#AEN36 3. file://localhost/tmp/@31281.2#AEN38 4. file://localhost/tmp/@31281.2#AEN58 5. file://localhost/tmp/@31281.2#AEN61 6. file://localhost/tmp/@31281.2#AEN68 7. file://localhost/tmp/@31281.2#AEN76 8. file://localhost/tmp/@31281.2#AEN80 9. file://localhost/tmp/@31281.2#AEN88 10. file://localhost/tmp/@31281.2#AEN91