gEDA: New open-source netlist translators...

[Bill Cox <bill-at-NOSPAMviasic_dot_com>]

Hi.

I've added a new Verilog netlister to gnetman, and a preliminary SPICE
reader.  In theory, any gnetman compatible symbols will come out in
either SPICE or Verilog format properly, including hierarchy, busses,
instance arrays, etc.

Eventually, I expect that gnetman will be capable of translating
structural Verilog, VHDL, SPICE (multiple formats), and EDIF back and
forth.  There will also probably be a native netlist format that is
expressive enough to represent the structural netlist constructs of all
the other formats.  Tentetively, it will be called FNF, for Free Netlist
Format.  Tom Hawkins and I have been discussing the nature of that
format.  It's main advantages are to be small size, ASCII based, simple
to read/write, and expressiveness.  It will also probably have an XNF
version, though that will be a bit more verbose.

The gnetman netlist manipulation system is currently, and will probably
remain, somewhat focused on very large designs, typically chip designs
or large FPGAs.

I'd also like to eventually see gnetman capable of creating schematics
for gschem as well as reading them (as it does now).  Without this
capability, it's tough to visualize what's in the database.  However, I
clearly don't have the bandwidth to tackle a schematic generator any
time soon.  The SoC Builder will probably be my next significant
open-source project.

I'm trying to also integrate a link into Confluence, so that CF can be
used for module generation.  The idea here is that generatable
components, like LPM instances, could be generated with CF programs.  It
is very common to have components at a structural netlist level that
still need to be generated, and CF seems perfect for the task.  This
could also be used as a mechanism to integrate CF with the SoC Builder,
since I expect to use gnetman for the SoC Builder's netlist database.

Bill